1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a memory element capable of erasing and reprogramming data electrically, and a method of retrieving a faulty in the nonvolatile semiconductor memory device, and more particularly to a semiconductor memory device having means for retrieving if a memory cell has a fault, and its test method, being used, for example, electrically erasable programmable read-only memory (EEPROM).
2. Description of the Related Art
As a memory cell for EEPROM, an NMOS transistor having a two-layer stack gate structure on a double well formed on a semiconductor substrate is formed in order to reduce in size.
FIG. 3 is a sectional view of an example of a cell composed of an NMOS transistor of two-layer stack gate structure.
In the diagram, reference numeral 30 is a P-type substrate (Psub), 31 is an N-type well (Nwell), and 32 is a P-type well (Pwell) formed in the N-type well. In the N-type well 31, a well extracting electrode is formed in an N+-type diffusion layer 33. In the P-type well 32, a source S and a drain D of the NMOS transistor are formed in an N+-type diffusion layer 34, and a well extracting electrode is formed in a P+-type diffusion layer 35.
On the substrate 30, a floating gate FG composed of a polycrystalline silicon layer of first layer is formed on a gate insulating film 36, and a control gate CG composed of a polycrystalline silicon layer of second layer is formed thereon, being separated by an insulating film 37.
In an actual semiconductor memory device, plural cells are arrayed in a matrix on the same well, and it is designed to select a certain cell by a plurality of word lines WL connected to the control gate CG of cell of each row and a plurality of bit lines BL connected to the drain D of cell of each row. Source lines SL are commonly connected to the source S, N-type well 31, and P-type well 32 of all cells.
The operation of the cell is briefly explained.
When erasing data, by applying, for example, 10V to the source line SL, 10V is applied to the source S, N-type well 31, and P-type well 32 of the cell. Further, by applying, for example, −7V to all word lines WL, −7V is applied to all control gates CG. The drain D is in a floating state. At this time, electrons in the floating gate FG are discharged into the channel by FN tunneling. In this state, the threshold of the cell is lowered, and the data in the erase state is called “1”.
When writing data, to select a cell desired to write in, any one of the plural word lines WL is set at, for example, 9V, any one of the plural bit lines BL is set at, for example, 5V, and the source line SL is set at 0V. At this time, in the selected cell, electrons are injected into the floating gate FG by hot electron injection. In this state, the threshold of the cell is high, and the data in the write state is called “0”.
When reading out data, to select a cell desired to read out, any one of the plural word lines WL is set at, for example, about 5V, any one of the plural bit lines BL is set at a low voltage (for example, about 0.7V), and the source line SL is set at 0V. At this time, when the selected cell is in a write state (data “0”), the cell is not turned on, and hence no current flows. By contrast, when the selected cell is in the erase state (data “1”), the cell is turned on, and a cell current of, for example, about 40 μA flows. The amplitude of this current is amplified by a sense amplifier (not shown) or the like and read out.
In this explanation of operation, the example is a memory cell of NOR type for erasing by applying a high voltage to the substrate side of the memory cell, however, a similar operation control is also possible in other type, such as a memory cell designed to erase by applying a high voltage to the source.
FIG. 4 shows an example of array of a memory chip region formed on a semiconductor wafer. In FIG. 4, one chip region is shown in an enlarged view, and an example of array of pads formed on the chip region is shown.
When manufacturing a semiconductor memory, while patterning each layer for composing a memory on one silicon wafer 40 by step-and-repeat technique, usually, hundreds to thousands of chip regions 41 are formed.
Among all chip regions 41, generally, there are several percent of defective chips not satisfying the desired characteristics due to effects of dust or fluctuations of processing of each layer for composing the memory, and it is hence necessary to sort out defective chips by testing all chip regions. To sort out chips, hitherto, when a defective chip is found, it is replaced by built-in retrieving means to a non-defective chip.
FIG. 5 shows an example of configuration of a conventional EEPROM comprising fault retrieving means in column unit.
A main memory cell array (MMA) 10 has main memory cells 11 arrayed in a matrix, and the main memory cell is selected by a row decoder (RD) 12, a column decoder (CD) 13, and a column selection gate (CG) 14.
A redundancy cell array (RMA) 15 has redundancy memory cells 16 arrayed in a column direction. When there is a faulty memory cell in the main memory cell array 10, the redundancy memory cell 16 is selected by the row decoder 12, redundancy column decoder and redundancy column selection gate (RCG) 17, so that the faulty memory cell in the main memory cell 11 can be replaced (retrieved) with the redundancy memory cell 16.
In reading operation of the main memory cell array 10, the data of the selected main memory cell is connected to j pieces of sense amplifiers (SAj) 19 through j pieces of data lines (DLj) 18 selected by the column selection gate 14, and read data SAOj are outputted.
In reading operation of the redundancy cell array 15, the data of the selected redundancy memory cell 16 is connected to k pieces of redundancy sense amplifiers (RSAk) 21 through k pieces of data lines (RDLk) 20 selected by the redundancy column selection gate 17, and read data RSAk are outputted.
One set of retrieve circuit is composed of a retrieve address memory circuit (RDFUSE) 22, a retrieve address latch circuit (RDLAT) 23, and a fault address detecting circuit (RDHIT) 24, and usually plural sets of retrieve circuits are provided.
The retrieve address memory circuit 22 comprises memory elements of same composition as, for example, the main memory cell 11 or redundancy memory cell 16, and receives an address signal RDADi from an address buffer (ADBF) 25, and is controlled by a write control signal RDPRG to store a retrieve address (i.e., a fault address). The retrieve address latch circuit 23 latches the retrieve address at the time of turning on the power. As the memory element of the retrieve address memory circuit 22, for example, metal fuse element or exclusive memory cell may be used.
The fault address detecting circuit 24 compares output RDi of the retrieve address latch circuit 23 and output RDADi from the address buffer 25. When input of fault address is detected, a column hit signal HITCOL becomes “H”, and a replacement information signal HITIO for specifying the redundancy sense amplifier 21 is outputted.
An output multiplexer (MUX) 26 receives the column hit signal HITCOL and replacement information signal HITIO, and replaces output SAOj of the sense amplifier 19 with output RSAOk of the predetermined redundancy sense amplifier 21 to output as DSj. When this DSj is outputted to an external terminal through an output buffer (not shown), the fault address is retrieved in the column unit.
A method of retrieving a faulty in a memory chip region on a wafer shown in FIG. 4 is explained below.
When sorting out the chips, all memory cells on the chip region 41 must be tested for writing, erasing and reading, and the time spent for this test causes to increase the manufacturing cost of the memory. Accordingly, various techniques have been attempted to shorten the memory test time, and one of such techniques is simultaneous testing of plural chip regions 41 on the silicon wafer 40 as one unit.
In the case of sorting test, various tests are conducted with plural probes of a sorting tester (not shown) fitted simultaneously to plural pads on the chip region 41. At this time, by fitting probes simultaneously to plural chip regions 41 of one unit, signals are transmitted from the sorting tester simultaneously to corresponding pads of each chip region 41, and plural chip regions 41 of one unit are tested in parallel operation.
In the sorting tester, the tester main body and tester probes are coupled through a relay circuit (not shown) for controlling connection and disconnection. The chip region 41 judged to be faulty before fault retrieval is disconnected by the relay circuit, and is not tested further, and adverse effects (voltage drop, etc.) of faulty chips are eliminated.
In such sorting test, however, when testing plural chip regions 41 simultaneously and retrieving a fault, writing time of fault address is long, and the test time is long.
That is, since the fault address to be retrieved usually varies in each chip, and the fault address is written in every chip by controlling the relay circuit of sorting tester. At this time, a setting time of about tens of milliseconds is needed every time when changing over the relay circuit.
The chip region 41 usually contains about tens to hundreds of retrieve circuits RDCIR. Assuming, for example, 100 pieces of RDCIR are contained in each chip region, it takes the time of about 10 ms×100 pieces=1 s is needed for writing the fault address into the retrieve address memory circuit RDFUSE of the retrieve circuit RDCIR. As the writing time of each address, for example, the time of about 100 μs is needed individually.
Further, as mentioned above, in the testing method of sending signals simultaneously to the chip regions 41 in a state in which tester probes are fitted simultaneously to plural chip regions 41 of one unit, individual chip regions 41 cannot be tested independently, and simultaneous measurement is impossible in the case of requirement of different controls in each chip region 41 as in the case of writing of fault address.
To test individual chip regions 41 independently, it is possible by connecting the relay circuit to one chip region 41 only, but it not only leads to increase of test time, but also requires modification or purchase of testers, and hence the manufacturing cost is increased.
In the conventional EEPROM, as mentioned above, if attempted to measure plural chip regions simultaneously for retrieving faults in the wafer stage, the writing time of fault address for fault retrieval is long, the test time is long, and hence the manufacturing cost is higher.